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QikData

Significant design elements were:

  • Integration of Altera PCI 64/66 IP core.
  • Scatter/Gather Direct Memory Access (DMA) assisted in OS compatibility.
  • LVDS based cabled bus using proprietary protocol. The protocol was designed for low latency maximum throughput through a novel scheme of flow-through data that did not require any store and forward packet buffers.
  • FPGA based NIOS processing core was utilised. Chip and pin count was reduced and permits the field upgrade of not only firmware but also hardware functions.
  • IDE interface and controller was implemented in FPGA and CPLD logic.
  • SDRAM controller with Error Checking and Correction (ECC).
  • Surface mount, high pin density, controlled impedance PCB design
  • Battery charge and capacity monitoring







Level 3, 25 King Street
Rockdale NSW 2216
Phone 9599 3255

Issue 160313